This test reads and clears the port’s Receive FIFO error counter maintained on the circuit pack. This counter is incremented by the circuit pack when it detects an overflow of its receive buffers. The test passes if the value of the counter is 0 (that is, the error is cleared). If the counter is not zero, the test fails, and the value of the counter is displayed in the Error Code field.
This error can occur if signaling frames are being received from a packet bus at a rate sufficient to overflow the receive buffers on the circuit pack for a port or if a hardware fault is causing the receive buffers not to be emptied properly. This test is useful for verifying the repair of the problem. This test runs on the following maintenance objects:
